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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
PI74FCT16511T PI74FCT162511T
Product Features:
Common Features: * PI74FCT16511 and PI74FCT162511 are high-speed, low power devices with high current drive. * Vcc = 5V 10% * Typical tsk(o) (Output Skew) < 250 ps, clocked mode * Extended range of -40C to +85C * Hysteresis on all inputs * Packages available: - 56-pin 240 mil wide TSSOP (A) - 56-pin 300 mil wide SSOP (V) PI74FCT16511T Features: * High output drive: IOH = -32 mA; IOL = 64 mA * Power off disable outputs permit "live insertion" * Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C PI74FCT162511T Features: * High output drive: IOL/IOH = 24 mA * Open drain parity error allows wire-OR * Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C * Balanced output drivers: 24 mA * Series current limiting resistors
Fast CMOS 16-Bit Registered/Latched Transceiver With Parity
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are produced in the Company's advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16511T and PI74FCT162511T are high-speed, lowpower 16-bit registered/latched transceiver with parity which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. It has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. One error flag for each direction (A-to-B or B-to-A) exists to indicate an error for either byte in either direction. The parity error flags which are open drain outputs, can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. To disable the error flag during combinational transitions, a designer can disable the parity error flag by the OExx control pins. The operation in A-to-B direction is controlled by LEAB, CLKAB and OEAB control pins, and the operation in B-to-A direction is controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK is used to select the operation of A-to-B direction, while B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Independent operation can be achieved between the two directions by using the corresponding control lines except for the ODD/EVEN control.
Simplified Logic Block Diagram
LEAB CLKAB Data Parity, data 16 Parity GEN/CHK Byte Parity Generator/ Checker 2 Latch/ Register 18 B0-15 PB1,2 PERB (Open Drain) OEAB
A0-15 PA1,2 ODD/EVEN
LEBA CLKBA Parity, data 18 OEBA PERA (Open Drain) Latch/ Register Byte Parity Checking Parity, data 18
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Logic Block Diagram
ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB A0-A7 C D C C D D OEBA P C O PA1 D I C C D D C A8-A15 D C C D D C D B8-B15 P D C PB1 C D B0-B7
P C O PA2 D I C C D D C GEN/CHK D C PERA (Open Drain) C D D P C D (Open Drain) PERB D C PB2
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Product Pin Description
Pin Name
OEAB OEBA CLKAB CLKBA LEAB LEBA PERA PERB Ax Bx ODD/EVEN(1) GEN/CHK(1) PAx(2) PBx GND VCC
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Product Pin Configuration
OEAB LEAB PA1 GND A0 A1 VCC A2 A3 A4 A5 A6 A7 GND PERA A8 A9 A10 A11 A12 A13 VCC A14 A15 GND PA2 OEBA LEBA
Description
A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Clock Input B-to-A Clock Input A-to-B Latch Enable Input B-to-A Latch Enable Input Parity Error (Open Drain) on A Outputs Parity Error (Open Drain) on B Outputs A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or B-to-A 3-State Outputs Parity Mode Selection Input A-to-B Port Generate or Check Mode Input A-to-B Parity Input, B-to-A Parity Output B-to-A Parity Input, A-to-B Parity Output Ground Power
1 2 3 4 5 6 7 8 9 10 11 12 56-PIN V56 13 A56 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GENCHK CLKAB PB1 GND B0 B1 VCC B2 B3 B4 B5 B6 B7 PERB GND B8 B9 B10 B11 B12 B13 VCC B14 B15 GND PB2 CLKBA ODD/EVEN
NOTES: 1. ODD/EVEN and GEN/CHK should be tied to VCC or GND with no resistor for optimum results. 2. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A-to-B direction, there is no need to add a pull-up resistor to guarantee state. The pin will still function properly as the parity output for the B-to-A direction.
Capacitance (TA = 25C, f = 1 MHz)
Parameters(1) CIN CI/O CO Description Input Capacitance I/O Capacitance Open Drain Capacitance Test Conditions VIN = 0V VOUT = 0V VOUT = 0V Typ 4.5 5.5 4.5 Max. 6.0 8.0 6.0 Units pF pF pF
Note: 1. This parameter is determined by device characterization but is not production tested.
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Truth Table (Parity Generation) (1, 2, 3, 4, 5)
A0 - A7, Total Number of Inputs that are high
1, 3, 5 or 7 1, 3, 5 or 7 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8
Truth Table (Parity Checking) (1, 2, 3, 4)
A0 - A7 and PA1(5), Total Number of Inputs that are high
1, 3, 5, 7 or 9 1, 3, 5, 7 or 9 0, 2, 4, 6 or 8 0, 2, 4, 6 or 8
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Truth Table(1,2)
Inputs LEAB CLKAB X X H X H X L L L L L H Output Buffers BX Z L H L H B(3) B(4)
OEAB H L L L L L L
AX X L H L H X X
NOTES: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care or Irrelevant Z = High Impedance = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A flow control is the same, except using OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, assuming CLKAB was HIGH before LEAB went LOW.
ODD/EVEN
L H L H
PB1
H L L H
NOTES: 1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H. 2. A-to-B parity generation is shown. B-to-A can check parity while A-to-B is performing generation. B-to-A will not generate parity. 3. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock. 4. Conditions shown are for the byte A0-A7. The byte A8-A15 is similar but will output the parity on PB2. 5. The error flag PERB will remain in a high state during parity generation.
ODD/EVEN
L H L H
PERB
L H(6) H(6) L
NOTES: 1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A parity checking is same but uses OEBA = L, OEAB = H and errors will be indicated on PERA. 3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB1 = PA1) 4. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock. 5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and PA2 is same. 6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-A15. If a parity error occurs on either byte PERB will go low.
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................................... -65C to +150C Ambient Temperature with Power Applied .................................... -40C to +85C Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. -0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ........... -0.5V to +7.0V DC Input Voltage ............................................................................ -0.5V to +7.0V DC Output Current ..................................................................................... 120 mA Power Dissipation ..........................................................................................1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 5.0V 10%)
Parameters Description VIH VIL IIH IIL IOZH IOZL VIK IOS IO IOFF VH Input HIGH Voltage Input LOW Voltage Input HIGH Current (Input pins) (I/O pins) Input LOW Current (Input pins) (I/O pins) High Impedance Output Current Clamp Diode Voltage Short Circuit Current (I/O pins) Output Drive Current (I/O pins) Output Leakage Current (Open Drain) Input Hysteresis Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VIN = VCC VCC = Max. VCC = Max. VCC = Min., IIN = -18 mA VCC = Max.(3), VOUT = GND VCC = Max.(3), VOUT = 2.5V VCC = Max., VOUT = 4.5V VIN = GND VOUT = 2.7V VOUT = 0.5V -80 -50 -0.7 -140 Min. 2.0 0.8 1 -1 1 -1 1 -1 -1.2 -225 -180 100 Typ(2) Max. Units V V A A A A V mA mA A mV
100
PI74FCT16511T Output Drive Characteristics (Over the Operating Range)
Parameters Description VOH Output HIGH Voltage Test Conditions(1) VCC = Min., VIN = VIH or VIL IOH = -3.0 mA IOH = -15.0 mA IOH = -32.0 mA IOL = 64 mA Min. 2.5 2.4 2.0 -- Typ(2) 3.5 3.5 3.0 0.2 -- Max. Units V
VOL IOFF
Output LOW Voltage Power Down Disable
VCC = Min., VIN = VIH or VIL VCC = 0V, VIN or VOUT 4.5V
0.55 100
V A
PI74FCT162511T Output Drive Characteristics (Over the Operating Range)
Parameters VOH VOL IODL IODH Description Output HIGH Voltage Output LOW Voltage Output LOW Current Output HIGH Current Test Conditions(1) VCC = Min., VIN = VIH or VIL IOH = -24.0 mA VCC = Min., VIN = VIH or VIL IOL = 24 mA VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) Min. 2.4 60 -60 Typ(2) 3.3 0.3 115 -115 Max. 0.55 150 -150 Units V V mA mA
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Power Supply Characteristics
Parameters Description ICCL, ICCH, Quiescent Power ICCZ Supply Current ICC ICCD Supply Current per Input @ TTL HIGH Supply Current per Input per MHz(4) Test Conditions(1) VCC = Max. VCC = Max. VIN = GND or VCC VIN = 3.4V(3) Min. Typ(2) 0.1 0.5 75 Max. 500 1.5 120 Units A mA A/ MHz
VCC = Max., Outputs Open VIN = VCC OEAB = GND VIN = GND OEBA = VCC One Bit Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10 MHZ (CLKAB) 50% Duty Cycle LEAB = OEAB = GND OEBA = VCC fI = 5 MHZ One Bit Toggling VCC = Max., Outputs Open fCP = 10 MHZ (CLKAB) 50% Duty Cycle LEAB = OEAB = GND OEBA = VCC fI = 2.5 MHZ 18 Bits Toggling VIN = VCC VIN = GND
IC
Total Power Supply Current(6)
0.8
1.7(5)
mA
VIN = 3.4V VIN = GND
1.3
3.2(5)
VIN = VCC VIN = GND
3.8
6.5(5)
VIN = 3.4V VIN = GND
9.0
21.8(5)
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + FINI) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz.
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
16511T/162511T Switching Characteristics over Operating Range (Propagation Delays)
16511/162511T Com. 162511AT Com. Max Min Max Unit
Parameters tPLH tPHL tPLH tPHL tPLH tPHL tPLH(3) tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPLH tPHL tPLH(3) tPHL tPZH tPZL tPHZ tPLZ tPLZ(3) tPZL tPLH tPHL tPLH tPHL
Description Propagation Delay PAx to PBx Propagation Delay Ax to Bx or Bx to Ax, PBx to PAx Propagation Delay Ax to PBx Propagation Delay Ax to PERB, PAx to PERB Propagation Delay Bx to PERA, PBx to PERA Propagation Delay LEBA to Ax and PAx LEAB to Bx and PBx Propagation Delay LEBA to PERA, LEAB to PERB Propagation Delay CLKBA to Ax and PAx CLKAB to Bx and PBx Propagation Delay CLKBA to PERA CLKAB to PERB Output Enable Time OEBA to Ax and PAx OEAB to Bx and PBx Output Disable Time(4) OEBA to Ax and PAx OEAB to Bx and PBx Parity ERROR Enable OEBA to PERA, OEAB to PERB ODD/EVEN to PERB ODD/EVEN to PBx
Conditions(1) CL = 50 pF RL = 500
Min
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
6.5 6.5 9.0 10.5 9.5 10.5 9.5 6.0
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
5.7 5.0 7.5 9.0 8.0 9.0 8.0 5.6
ns ns ns ns ns ns
1.5 1.5 1.5
7.5 6.5 6.0
1.5 1.5 1.5
7.0 6.0 5.6
ns ns
1.5 1.5 1.5
7.5 6.5 7.0
1.5 1.5 1.5
7.0 6.0 6.0
ns
ns
1.5
7.0
1.5
5.6
ns
1.5 1.5 1.5 1.5 1.5
6.0 6.0 10.0 10.0 10.0
1.5 1.5 1.5 1.5 1.5
6.0 6.0 10.0 10.0 10.0
ns ns ns
Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. On Open Drain Outputs tPLH is measured up to VOUT = VOL + 0.3V. 4. This parameter is guaranteed but not production tested.
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PS2080A 01/15/95
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PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
PI74FCT16511T/162511T Switching Characteristics over Operating Range (Setup Times)
16511/162511T 162511AT
Com. Parameters tSU Description Setup Time HIGHorLOW Ax to CLKAB Setup Time PAx to CLKAB Setup Time Bx to CLKBA PBx to CLKBA Setup Time Ax to LEAB GEN/CHKLOW GEN/CHKHIGH GEN/CHKHIGH Conditions(1,3) PBx valid PBx not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid PBx valid PBx not valid PERB valid PERB not valid PBx valid PBx not valid PERB valid PERB not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid PERA valid PERA not valid Min. 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 6.5 3 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Com. Min. 4 3 4 3 4 3 4 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 3.5 3 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSU tSU
tSU
tSU
Setup Time PAx to LEAB
tSU
Setup Time Bx to LEBA PBx to LEBA
CLKAB LOW GEN/CHK LOW CLKAB LOW GEN/CHK HIGH CLKAB HIGH GEN/CHK LOW CLKAB HIGH GEN/CHK HIGH CLKAB LOW GEN/CHK HIGH CLKAB HIGH GEN/CHK HIGH CLKBA LOW CLKAB HIGH
CL = 50 pF RL = 500
PI74FCT16511T/162511T Switching Characteristics over Operating Range (Hold Times)
16511/162511T16511/162511AT Com. Com.
Parameters tH tH tH tH tH tW tW
Description Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time HIGH or LOW PAx to LEAB Hold Time HIGH or LOW PBx to LEBA Hold Time Ax to CLKAB, PAx to CLKAB Hold Time Bx to CLKBA, PBx to CLKBA LEAB or LEBA Pulse Width HIGH(2) CLKAB or CLKBA Pulse Width HIGH or LOW(2)
Conditions(1)
Min. 1 1 1 1 1 3 3
Max. -- -- -- -- -- -- --
Min. 1 1 1 1 1 3 3
Max. -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns
CL = 50 pF RL = 500
Notes: 1. See test circuit and wave forms. 2. This parameter is guaranteed but not production tested. 3. "Not valid" means the setup time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the A-to-B or B-to-A port respective to the indicated direction. Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS2080A 01/15/95

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